1. Field of the Invention
The present invention relates to receiver circuits responsive to small signal level signals such as emitter-coupled-logic (ECL) level signals for converting the small level signals to larger signal swings such as used for to FET logic levels, and more particularly, to an ECL receiver circuit including a source-follower stage.
2. Background Art
U.S. Pat. No. 4,264,829 issued Apr. 28, 1981 to Misaizu entitled MOS INVERTER-BUFFER CIRCUIT HAVING A SMALL INPUT CAPACITANCE and a continuation, U.S. Pat. No. 4,446,387 issued May 1, 1984, describes a circuit for preventing an input signal supplied to an input terminal from directly affecting an inverted signal derived at a node. An inverter stage of an inverter-buffer circuit composed of MOS transistors comprises two additional partial inverter stages between a buffer stage and a conventional inverter stage that serves as an input-side partial inverter stage. The buffer stage comprises an additional MOS transistor having a gate connected directly to the node in order to achieve a short switching delay.
Other prior art includes U.S. Pat. No. 4,096,398 issued June 20, 1978 to Khaitan entitled MOS OUTPUT BUFFER CIRCUIT WITH FEEDBACK and relating to a PMOS output buffer circuit which permits interfacing directly with TTL, CMOS and NMOS. A feedback circuit incorporated into the buffer acts to limit the drive current for negative potential output excursions. The feedback circuit is sensitive to device parameters that vary with processing so that the output characteristics can be set independently of process variables.
U.S. Pat. No. 4,316,106 issued Feb. 16, 1982 to Young et al entitled DYNAMIC RATIOLESS CIRCUITRY FOR RANDOM LOGIC APPLICATIONS describes a logic circuit for receiving an input signal and for generating a delayed output signal being clocked by first and second non-overlapping clock phases. The logic circuit includes a voltage supply, a precharge transistor interconnected to the voltage supply clocked by the first clock phase. A discharge transistor is interconnected to the precharge transistor thereby defining a first node and is clocked by the second clock phase to conditionally discharge the first node. An input logic circuit is interconnected to the discharge transistor, thereby defining a second node for providing a discharge path from the first node to a ground voltage potential, the input logic circuit is connected to receive the input signal. An output transistor is interconnected to the first node for generating the delayed output signal. The output transistor is clocked by the second clock phase. A capacitor is interconnected to the first node and the output transistor and is clocked by the second clock phase for maintaining the first node at a predetermined voltage level by a bootstrapping operation.
U.S. Pat. No. 4,521,701 issued June 4, 1985 to Reddy entitled HIGH-SPEED LOW-POWER DELAYED CLOCK GENERATOR describes a clock circuit for producing a high-level delayed clock output following an input clock employing an output transistor and pull-down transistor controlling an output node in response to the voltage on a drive node. The input node clock is applied to this drive node by a decoupling arrangement, consisting of two series transistors. The first transistor isolates the input charge on a holding node, and the second of the series transistors transfers the charge to the drive node after the desired delay. The output node is held at zero until after the delay, with no unwanted voltage rise, and no d.c. power loss. A large capacitive load can be driven.
U.S. Pat. No. 4,542,307 issued Sept. 17, 1985 to Baba entitled DOUBLE BOOTSTRAPPED CLOCK BUFFER CIRCUIT describes a buffer circuit having first and second bootstrap circuits. The first bootstrap circuit charges the gate of an output MOS transistor to a voltage above a supply voltage when an input signal has a first logic level. The gate of a precharging MOS transistor in the first bootstrap circuit is driven by the second bootstrap circuit so as to precharge a capacitor in the first bootstrap circuit to a voltage above the supply voltage when the input signal has a second logic level.
U.S. Pat. No. 4,554,469 issued Nov. 19, 1985 to Segawa et al entitled STATIC BOOTSTRAP SEMICONDUCTOR DRIVE CIRCUIT describes a semiconductor circuit having a static bootstrap circuit, which includes a first MOS transistor with an input signal supplied to the gate and having the current path connected between a voltage source terminal and a node, a second MOS transistor having the gate connected to receive an inverted form of the input signal after a delay time and having the current path connected between the node and a reference potential terminal and a capacitor connected between the gate of the first MOS transistor and the node. The semiconductor circuit also has a short pulse generator. The bootstrap circuit further includes a third MOS transistor having the current path connected between the output terminal of the short pulse generator and the node and with the input signal supplied to the gate and fourth and fifth MOS transistors having the respective gates connected to the gates of the first and second MOS transistors and the respective current paths connected in series between the voltage source terminal and reference potential terminal.
In Electronics, Sept. 9, 1985, at page 94 an article describes an ECL to CMOS interface which uses BIMOS, a mixture of CMOS and bipolar technology to manufacture a single memory chip. The multiple process steps of integrating bipolar and CMOS technologies is necessarily complex and expensive and thus undesirable.
Another example of a bipolar logic level to FET logic level interface circuit is described in IBM Technical Bulletin, Volume 19, No. 8, January 1977, pages 2953-2954. This circuit provides a clocked circuit for receiving input ECL or TTL logic levels. This circuit requires three timing signals to couple the logic signals on the input modes to higher voltages suitable for driving an FET array. No method for converting the timing signals from ECL levels to the required FET voltage levels is given.
An example of an ECL to CMOS interface circuit using only CMOS devices is described in the Extended Abstracts of the 17th Conference on Solid State Devices and Materials, Tokyo, 1985, pp. 53-56. This interface circuit uses an input stage to shift the ECL signal by an adjustable amount in order to drive a standard CMOS inverter.
In U.S. Pat. No. 4,645,954 entitled ECL TO FET INTERFACE CIRCUIT FOR FIELD EFFECT TRANSISTOR ARRAYS, issued Feb. 2, 1987 in the name of S. E. Schuster, an interface circuit for coupling bipolar logic circuit output signals to an FET logic array is described. The interface receives chip select signals and their complement on a dual-rail input line. A small signal amplifier comprising an FET amplifier having an input FET transistor connected through its source and gate to the dual-rail input terminals, converts the chip enable signal to a high level clocking signal. An FET dynamic sense amplifier receives a bipolar logic level to be converted to an FET logic level, and receives a reference level from the bipolar transistor logic circuit. Upon clocking of the dynamic sense amplifier by the small signal multiplier, the true and complementary FET logic levels corresponding to the input bipolar logic levels are provided by the dynamic sense amplifier.
In copending patent application entitled INTERFACE CIRCUIT INCLUDING A LEVEL SHIFTING AND MULTIPLYING CIRCUIT FOR AN INTERFACE CIRCUIT BETWEEN TRANSISTOR LOGIC LEVELS AND EFFECT TRANSISTOR LOGIC LEVELS, Ser. No. 06/825,420, filed Feb. 3, 1986 in the name of S. E. Schuster et al, field effect transistor (FET) circuits for converting input ECL transistor logic levels to FET logic levels are described. More particularly, an FET interface circuit including an enhancement device which converts either a dual-rail or a single-rail ECL chip select signal to an FET voltage level and single-rail ECL address and data-in signals to true and complement FET voltage levels is described for use in FET semiconductor memories.